//`include "SimTop.v"
`include "handshake_pipe.v"
//~ `New testbench
`timescale  1ns / 1ps

module testbench (
    
    );

    reg clk = 0, rst = 1;

    reg [31:0] master_data = 0;
    reg master_valid       = 0;
    wire master_ready         ;

    wire slave_valid          ;
    wire [31:0] slave_data    ;
    reg slave_ready        = 0;

    parameter period = 10;

    initial begin
        clk = 0;
        forever #(period/2) clk = ~clk;
    end

    initial begin
        #period rst = 0;
    end

    handshake_pipe handshake_pipe0 (
        .clk(clk),
        .rst(rst),
        
        .master_valid(master_valid),
        .master_data(master_data),
        .master_ready(master_ready),

        .slave_valid(slave_valid),
        .slave_data(slave_data),
        .slave_ready(slave_ready)
    );

    integer i = 1 ;

    initial begin
        master_data  = 1;
        master_valid = 1;
    end

    always @(posedge clk) begin
        if(master_ready) begin
            master_data <= master_data + 1;
        end
    end

    integer j = 0;
    always @(posedge clk) begin
        j <= j+1;
        if(0<j && j<3 ) begin
            slave_ready <= 1;
        end
        else if(3<=j && j<8) begin
            slave_ready <= ~slave_ready;
        end
        else if(8<=j && j<=11) begin
            slave_ready <= 0;
        end
        else begin
            slave_ready <= 1;
        end
        if(j>50) $finish;
    end


    initial begin
        $dumpfile("wave.vcd"); // 指定用作dumpfile的文件
		$dumpvars; // dump all vars
	end

endmodule //testbench